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UTRON
Rev. 1.5 FEATURES
Access time : 35/55/70ns (max.) Low power consumption : Operating : 60/50/40 mA (typical) Standby : 2A (typical) L-version 1A (typical) LL-version Single 5V power supply All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 32-pin 600 mil PDIP 32-pin 450 mil SOP 32-pin 8mmx20mm TSOP-1 32-pin 8mmx13.4mm STSOP
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT621024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT621024 is designed for low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT621024 operates from a single 5V power supply and all inputs and outputs are fully TTL compatible.
PIN CONFIGURATION
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2
WE
FUNCTIONAL BLOCK DIAGRAM
A16 A15 A13 A14 A12 A7 A6 A5 A4 A8
ROW DECODER
A16 A14 A12
.
MEMORY ARRAY
VCC
A7 A6 A5 A4 A3
A13 A8 A9 A11
OE
UT621024
. .
1024 ROWS x 1024 COLUMNS
VSS
A2 A1 A0 I/O1 I/O2
A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
.
I/O1 . . I/O8
.
.
I/O3 Vss
. . .
.
I/O CONTROL
. . .
COLUMN I/O COLUMN DECODER
A11
PDIP / SOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
CE 1
CE2 WE OE
LOGIC CONTROL
OE
A10
A10 A11 A9 A3 A2 A1 A0
A9 A8 A13
CE 1
I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 A3
WE
PIN DESCRIPTION
SYMBOL A0 - A16 I/O1 - I/O8 CE1 ,CE2 WE OE VCC VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable 1,2 Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4
UT621024
25 24 23 22 21 20 19 18 17
TSOP-I/STSOP
________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
Rev. 1.5 ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
RATING -0.5 to +7.0 0 to +70 -65 to +150 1 50 260 UNIT V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Standby Output Disable Read Write CE1 H X L L L CE2 X L H H H OE X X H L X
WE X X H H L
I/O OPERATION High - Z High -Z High - Z DOUT DIN
SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC ICC ICC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, TA = 0 to 70)
PARAMETER SYMBOL TEST CONDITION Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIL VSS VIN VCC Output Leakage Current IOL VSS VI/OVCC
MIN. TYP. MAX.
2.2 - 0.5 -1
60 50 40 2 1
VCC+0.5 0.8 1 1 0.4 100 85 70 10 3 100 40* 50 15*
UNIT V V A A V V mA mA mA mA mA A A
Output High Voltage Output Low Voltage Average Operating Power Supply Courrent
VOH VOL ICC
ICC1
CE1 =VIH or CE2 = VIL or -1 OE = VIH or WE = VIL IOH = - 1mA 2.4 IOL= 4mA Cycle time=min, 100% duty, -35 -55 CE1 =VIL, CE2 = VIH, II/O = 0mA -70 Cycle time=1s,100% duty,II/O=0mA . CE1 0.2V,CE2VCC-0.2V, other pins at 0.2V or VCC-0.2V, CE1 =VIH or CE2 = VIL other pins at 0.2V or VCC-0.2V, CE1 VCC-0.2V or -L .CE20.2V other pins at 0.2V or VCC-0.2V, LL -
Standby Power Supply Current
ISB ISB1
*Those parameters are for reference only under 50
________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
Rev. 1.5 CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
-
MAX. 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL=100pF, IOH/IOL=-1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10% , TA = 0 to 70)
(1) READ CYCLE PARAMETER UT621024-35 UT621024-55 UT621024-70 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 35 55 70 ns Address Access Time tAA 35 55 70 ns Chip Enable Access Time tACE1, tACE2 35 55 70 ns Output Enable Access Time tOE 25 30 35 ns Chip Enable to Output in Low-Z tCLZ1*, tCLZ2* 10 10 10 ns Output Enable to Output in Low-Z tOLZ* 5 5 5 ns Chip Disable to Output in High-Z tCHZ1*, tCHZ2* 25 30 35 ns Output Disable to Output in High-Z tOHZ* 25 30 35 ns Output Hold from Address Change tOH 5 5 5 ns SYMBOL
(2) WRITE CYCLE PARAMETER
SYMBOL
Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write-Time Output Active from End of Write Write to Output in High-Z
tWC tAW tCW1, tCW2 tAS tWP tWR tDW tDH tOW* tWHZ*
UT621024UT621024-70 UNIT UT621024-55 35 MIN. MAX. MIN. MAX. MIN. MAX. 35 55 70 ns 30 50 60 ns 30 50 60 ns 0 0 0 ns 25 40 45 ns 0 0 0 ns 20 25 30 ns 0 0 0 ns 5 5 5 ns 15 20 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
Rev. 1.5 TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
tRC
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
Address
tAA tOH tOH
DOUT
Data Valid
READ CYCLE 2 ( CE1 , CE2 and OE Controlled) (1,3,5,6) tRC
Address
tAA
CE1
tACE1
CE2
tACE2
OE
tOE tCLZ1 tCLZ2
High-Z
DOUT
tOLZ
tCHZ1 tCHZ2 tOHZ tOH
Data Valid
High-Z
Notes : 1. WE is HIGH for read cycle. 2. Device is continuously selected CE1 =VIL and CE2=VIH. 3. Address must be valid prior to or coincident with CE1 and CE2 transition; otherwise tAA is the limiting parameter. 4. OE is low. 5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state. 6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
4
UTRON
Rev. 1.5
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
tWC Address
CE1
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
tAW
tCW1 CE2 tCW2 tAS tWP tWR
WE
tWHZ
High-Z
tOW (4) tDW tDH
DOUT
(4)
DIN
Data Valid
WRITE CYCLE 2 ( CE1 and CE2 Controlled) (1,2,5)
tWC Address
tAW
CE1
tAS
tCW1 tCW2
tWR
CE2
tWP
WE
tWHZ
High-Z
DOUT
(4) tDW tDH
DIN
Data Valid
Notes : 1. WE or CE1 must be HIGH or CE2 must be LOW during all address transitions. 2. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input singals must not be applied. 5. If the CE1 LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
5
UTRON
Rev. 1.5 DATA RETENTION CHARACTERISTICS (TA = 0 to 70)
PARAMETER Vcc for Data Retention Data Retention Current SYMBOL TEST CONDITION VDR CE1 VCC-0.2V or CE2 0.2V IDR Vcc=3V CE1 VCC-0.2V or CE2 0.2V See Data Retention Waveforms (below)
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
MIN. TYP. MAX. 2.0 -L - LL 0 tRC* 1 0.5 40 20* 20 10* -
UNIT V A A ns ns
Chip Disable to Data Retention Time Recovery Time
tCDR tR
tRC* = Read Cycle Time *Those parameters are for reference only under 50
DATA RETENTION WAVEFORM
Date Retention Mode
VCC
4.5V tCDR VDR 2.0V
4.5V tR VIH
CE1 VCC -0.2V
CE1 VSS CE2
VIH
VIL
CE2 0.2V
VIL
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
6
UTRON
Rev. 1.5 PACKAGE OUTLINE DIMENSION
32 pin 600 mil PDIP Package Outline Dimension
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
UNIT
SYMBOL
A
A
A1 A2 B B1 c D E E1 e eB L S Q1
INCH(BASE) 0.010 (MIN) 0.150 0.005 0.018 0.005 0.050 0.005 0.010 0.004 1.650 0.005 0.600 0.010 0.544 0.004 0.100(TYP) 0.640 0.020 0.130 0.010 0.075 0.010 0.070 0.005
MM(REF) 0.254 (MIN) 3.810 0.127 0.457 0.127 1.270 0.127 0.254 0.102 41.910 0.127 15.240 0.254 13.818 0.102 2.540(TYP) 16.256 0.508 3.302 0.254 1.905 0.254 1.778 0.127
Note: 1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
7
UTRON
Rev. 1.5
32 pin 450mil SOP Package Outline Dimension
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
UNIT
SYMBOL
A A1 A2 b c D E E1 e L L1 S y
A
A
C
INCH(BASE) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.015(MIN) 0.020(MAX) 0.008(TYP) 0.817(MAX) 0.445 0.005 0.555 0.005 0.050(TYP) 0.0347 0.008 0.055 0.008 0.026(MAX) 0.004(MAX) o o 0 -10
MM(REF) 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.38(MIN) 0.50(MAX) 0.203(TYP) 20.75(MAX) 11.303 0.127 14.097 0.127 1.270(TYP) 0.881 0.203 1.397 0.203 0.660 (MAX) 0.101(MAX) o o 0 -10
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
8
UTRON
Rev. 1.5
32 pin TSOP-I Package Outline Dimension
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
UNIT
SYMBOL
C
A A1 A2 b c D E e HD L L1 y
E
C
H B
INCH(BASE) 0.047 (MAX) 0.004 0.002 0.039 0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 0.004 0.315 0.004 0.020 (TYP) 0.787 0.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.20 (MAX) 0.10 0.05 1.00 0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 0.10 8.00 0.10 0.50 (TYP) 20.00 0.20 0.50 0.10 0.08 0.10 0.076 (MAX) o o 0 5
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
9
UTRON
Rev. 1.5
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
Uni t Symbol A A1 A2 b c D Db E e L L1 y e MM(REF) 1.20(Max.) 0.100.05 1.000.05 020(TYP.) 0.15(TYP.) 13.400.20 11.800.10 8.0000.10 0.50(TYP.) 0.500.10 0.800.10 0.08(Max.) 0 ~5 INCH(BASE) 0.047(Max). 0.0040.002 0.0390.002 0.006(TYP.) 0.006(TYP.) 0.5260.006 0.4650.004 0.3150.004 0.020(TYP.) 0.0200.004 0.03150.004 0.003(Max.) 0 ~5
Note 1.E dinmension is not including end flash. 2.The total of both sides' end flash Is not above 0.3mm.
________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
10
UTRON
Rev. 1.5 ORDERING INFORMATION
PART NO. UT621024PC-35L UT621024PC-35LL UT621024SC-35L UT621024SC-35LL UT621024LC-35L UT621024LC-35LL UT621024LS-35L UT621024LS-35LL UT621024PC-55L UT621024PC-55LL UT621024SC-55L UT621024SC-55LL UT621024LC-55L UT621024LC-55LL UT621024LS-55L UT621024LS-55LL UT621024PC-70L UT621024PC-70LL UT621024SC-70L UT621024SC-70LL UT621024LC-70L UT621024LC-70LL UT621024LS-70L UT621024LS-70LL ACCESS TIME (ns) 35 35 35 35 35 35 35 35 55 55 55 55 55 55 55 55 70 70 70 70 70 70 70 70 STANDBY CURRENT (A) 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50 100 50
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
PACKAGE 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
11
UTRON
Rev. 1.5
REVISION HISTORY REVISION REV. 1.0 REV. 1.1 REV. 1.2 REV. 1.3 REV. 1.4 REV. 1.5 DESCRIPTION Original. NA NA Add STSOP-I Package Modify the format of power consumption 1. Operating : 60/40 -> 60/50/40 2. Standby Current : 10 ->2 (L-version) 3. Add ICC-data as (-55, TYP 50, MAX 85) 4. Revise ISB1 TYP : 10-> 2, MAX : 300/100 ->100/40 5. The symbols CE1# ,OE# & WE# are revised as CE1 , OE & WE
UT621024
128K X 8 BIT LOW POWER CMOS SRAM
DATE Apr. 05 2000 --Aug. 29.2000 Sep. 01.2000 Jun. 18,2001
_________________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
12

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